Abstract
This paper studies the methodologies for developing dc fault-tolerant and highly efficient voltage-source converters (VSCs). Building on a recently proposed LCL-VSC converter, which suffers from low efficiency at partial load, an operating strategy of switchable capacitor banks instead of a fixed central capacitor is proposed to improve the efficiency. A theoretical framework is presented to enable LCL-VSC to achieve fault current limiting and avoid the blocking of insulated-gate bipolar transistors during dc faults. A design of traditional L-VSC (either two level or multilevel) that can limit fault current is also mathematically deduced as a comparison. The L-VSC can be designed to limit the fault current close to rated value, but this comes at an increase of around 40% in semiconductor costs and operating losses. The results show that the efficiency of LCL-VSC is similar to the conventional L-VSC. LCL-VSC cannot isolate dc faults, but their reduced fault current enables the converter to ride through dc faults and this significantly reduces the requirements on operating speed and capacity of dc circuit breakers. The LCL-VSC is especially suitable to replace conventional L-VSC at the grid points where a strong ac grid will feed significant dc fault current to the dc grid. Detailed PSCAD simulations confirm theoretical findings.
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