Layout-Induced Strain Study for RF Performance Improvement of 22-nm UTBB FDSOI PFET

Abstract

In this work, we study and characterize the layout-induced device strain and its impact on RF performance of 22-nm-ultrathin body and buried oxide fully depleted silicon-on-insulator (UTBB FDSOI) P-channel field-effect transistor (PFET). This will help in boosting and optimizing the RF performance for the targeted application. With shrinking device dimensions, conventional stress liners and embedded stressors used in strain-engineered CMOS devices become less effective. Therefore, intrinsically strained materials, such as compressively strained SiGe, are widely used to boost the holes' mobility in the channel. The stress level depends on both the manufacturing process and device geometry, and the optimization of these leads to improved dc and RF performances of PFET devices. We hereby study various layout parameters, such as width and length of the active region, contacted poly pitch, number of fingers, and source/drain contact, to maximize the channel uniaxial strain parallel to the current flow direction and, thus, improve the electrical performances. The studied layout parameters are then applied on sliced-active (RX) structures, which enables to achieve up to 30% improvement of both f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</sub> parameters of SiGe PFET with respect to a reference device. This also allows reducing the parasitic capacitance without significantly degrading the dc performance. The device strain modeling and physical characterization were conducted through the finite-element method (FEM) and nanobeam electron diffraction (NBED) in the transmission electron microscopy (TEM), respectively.