Layout Quality Criteria for CMOS Standard Cells of Digital IC

Abstract

The article is devoted to review and systematization of layout quality criteria for CMOS standard cells used as base core elements in EDA based digital IC design flows. Review of such criteria grouped by various quality aspects is given. It is shown with specific examples, that quality criteria of completed standard cell layouts can be used for a variety of purposes, including: analysis and quality control/assessment of standard cell libraries, identifying possibilities for layout improvements, and selecting the best variant of the layout among alternatives from different vendors (if available). Integral layout quality criterion, which enables flexible prioritization of different layout quality characteristics, is introduced. It is also proposed to use integral criterion for selecting between different layout versions of the same cell, obtained with different layout creation approaches. It is proposed to use branch-and-bound methodology based on quality criteria of partially completed (symbolic) layouts for selection from folded/placed/routed layout versions during the process of automated layout creation. Review of the criteria used for evaluating quality of the intermediate symbolic layouts during different stages of standard cell layout creation flow is also given in the article. Thus, with the thorough selection of intermediate layout versions the effectiveness of final layout is achieved. The results might be applied by standard cell libraries developers, but also by design engineers who should take a decision about different libraries usage based on comparative analysis.