Layout optimization of planar inductors for high-efficiency integrated power converters

Abstract

The performance of dc–dc power converters is critically dependent on the inductors at their core. Planar spiral inductors are compact constructions that can be scaled and integrated without the limitations of traditional wire-wound devices. Therefore, they are increasingly employed to meet the needs of modern low-power applications, especially where size, weight and manufacturing costs are deciding factors. As a planar inductor is designed to fit the parameters of an application, it is paramount to take into account the associated parasitic effects that have an impact on the converter performance. This paper analyzes how the conversion efficiency of boost and buck integrated power converters depends on the parasitics elements of planar inductors, and how it can be improved by optimizing the inductor layout. In particular, the paper provides the guidelines for maximizing the time constant of the inductor by considering the different geometrical features that define the inductor shape. The trade-offs that maximize the inductance time constant for different shapes are introduced, and an algorithm is developed to optimize the performance with no area overhead. Finally, three boost converters are designed, simulated, and compared in a 65-nm CMOS technology to demonstrate the validity of the proposed approach, and the corresponding conversion efficiency improvement is assessed.