Abstract
A layout technique to mitigate single-event transient (SET) is presented for monolithic 3D (M3D) integrated circuit through TCAD simulation. The effect of transistor- and gate-levels M3D on SET is investigated from the generation and propagation stages. The resulting SET characteristics show that transistor-level M3D exhibits stronger pulse quenching effect, thus higher priority than gate-level M3D and planar inverter in layout design. This results from the multi-nodes charge collection and multi-transistors charge collection. Placing PMOS above NMOS for transistor-level M3D is the optimal layout. Besides, through adjusting their physical distance and positions in the layout, the SET sensitivity is considerably reduced, as well as the chip area and static power consumption.
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