Layer-Aware Request Scheduling for 3D Flash-Based SSDs

Jinming Xu,Cong Ding,Yajuan Du

doi:10.1109/access.2021.3078720

Jinming Xu, Cong Ding + Show 1 more

Open Access

https://doi.org/10.1109/access.2021.3078720

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Abstract

Recent development on 3D flash memories largely promotes the wide application of Solid-State Drives (SSDs) by providing larger capacity from vertically-stacked layers. However, there exist speed variations across different layers because of manufacturing process variations or physical designs, which induces new challenges to fully explore the advantages of existing SSDs, e.g. the parallel structure. This paper investigates the effect of speed variation on the parallel performance of SSDs. To balance chips’ workloads, traditional method selects chips in a round-robin way. As chip queue time can be estimated by some main factors, the chip also can be chosen in a greedy way. However, because of the layer speed variation, queue time estimation model should be modified. This paper first establishes a new queue time estimation model with the awareness of the flash layer information. Then the model is used to estimate the chip queue time and to direct write requests into the chip with the least queue time. The key idea is to largely reduce queue time of each write, thus reducing the average SSD response time. Finally, this new request redirection method is evaluated on SSDsim with real world workloads. Experimental results show that our model can estimate the queue time more accurately and our new request redirection method can improve 8.3% of write queue time on average under the situation of 4 times speed variation among 16 layers.

Highlights

Multi-level parallelism of Solid State Drives (SSDs) plays an important role in SSD performance advantages [1], [2]
In order to verify the proposed chip queue time estimation model, this section presents the detailed design of our layer aware chip re-direction method, named as LaCR, which exploits the new model for more effective request dispatching and improved response time
2) Original chip redirection (OCR) is the method to allocate write sub-requests according to queue time estimation without the consideration of layer speed variations

Summary

INTRODUCTION

Multi-level parallelism of Solid State Drives (SSDs) plays an important role in SSD performance advantages [1], [2]. Liu et al [16] pointed that 3D flash memory suffered from reduced utilization of chip-level parallelism when the layer information is added, inducing sub-optimal parallel performance. From these works, it can be found that delay is an important metric for SSD parallel performance and many of these works use a method to estimate delay values. By exploiting the layer speed variation characteristic of 3D flash memory, this paper first establishes a layer-speed aware access time estimation method, and use this model to provide more accurate chip queue time judgment in advance, i.e. computing the sum of estimated access time for requests in each chip.

BACKGROUND

THEORETICAL MODEL

EVALUATION

EXPERIMENTAL SETUP

RELATED WORK

CONCLUSION