Lattice FIR digital filter architectures using stochastic computing

Abstract

This paper presents novel architectures for linear-phase FIR digital filters using stochastic computing. Stochastic computing systems require fewer logic gates and are inherently fault-tolerant. Thus, these structures are well suited for nanoscale CMOS technologies. Compared to direct-form linear-phase FIR filters, linear-phase lattice filters require twice the number of multipliers but the same number of adders. The hardware complexities of stochastic implementations of linear-phase FIR filters for direct-form and lattice structures are comparable. Using speech signals from ICA ′99 Synthetic Benchmarks, it is shown that, for linear-phase FIR filters, the error-to-signal power ratios of stochastic direct-form and stochastic lattice filters are about the same. However, the error-to-signal power of stochastic direct-form or lattice filter is an order of magnitude higher at very low fault rates but is more than two orders of magnitude less when the fault rate is about one percent than the direct-form, where the faults represent random bit-flips at outputs of all logic gates.