LaTiON/LaON as band-engineered charge-trapping layer for nonvolatile memory applications

X D Huang,P T Lai,Johnny K O Sin

doi:10.1007/s00339-012-6881-y

X D Huang, P T Lai + Show 1 more

Open Access

https://doi.org/10.1007/s00339-012-6881-y

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Journal: Applied physics	Publication Date: Mar 24, 2012
Citations: 8	License type: cc-by

Affiliation: University of Hong Kong

Abstract

Charge-trapping characteristics of stacked LaTiON/LaON film were investigated based on Al/Al2O3/LaTiON-LaON/SiO2/Si (band-engineered MONOS) capacitors. The physical properties of the high-k films were analyzed by X-ray diffraction, transmission electron microscopy and X-ray photoelectron spectroscopy. The band profile of this band-engineered MONOS device was characterized by investigating the current-conduction mechanism. By adopting stacked LaTiON/LaON film instead of LaON film as charge-trapping layer, improved electrical properties can be achieved in terms of larger memory window (5.4 V at ±10-V sweeping voltage), higher program speed with lower operating gate voltage (2.1 V at 100-μs +6 V), and smaller charge loss rate at 125 °C, mainly due to the variable tunneling path of charge carriers under program/erase and retention modes (realized by the band-engineered charge-trapping layer), high trap density of LaTiON, and large barrier height at LaTiON/SiO2 (2.3 eV).

Highlights

Floating-gate nonvolatile memory devices are rapidly approaching the scaling limit mainly due to their difficultyMONOS capacitor with an Al/Al2O3/LaTiON-LaON/SiO2/ Si structure was fabricated on p-type silicon substrate
The samples went through a post-deposition annealing (PDA) in N2 ambient at 850 °C for 30 s
The physical characteristics of the high-k dielectric films were characterized by X-ray diffraction (XRD), transmission electron microscopy (TEM) and X-ray photoelectron spectroscopy (XPS)

Summary

Introduction

Floating-gate nonvolatile memory devices are rapidly approaching the scaling limit mainly due to their difficultyMONOS capacitor with an Al/Al2O3/LaTiON-LaON/SiO2/ Si structure was fabricated on p-type silicon substrate. For a conventional MONOS memory device, it tends to have thinner tunneling oxide for higher program/erase (P/E) speeds and lower operating voltages, whereas a thinner tunneling oxide may deteriorate its retention property.

Results

Conclusion