Lateral PNP GaAs bipolar transistor with minimized substrate current

Abstract

Lateral pnp bipolar transistors have been fabricated using Be implantation to define the emitter and collector areas. The base area (1 - 2 µm wide) has been protected against Be ions during implantation by SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> and photoresist. The lateral straggling and diffusion during the anneling process reduces the base width, which can be adjusted with the annealing temperature and time. Between the active n-GaAs layer and substrate, a n-Ga <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7</inf> Al <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</inf> As layer is deposited. The Be ions penetrating the GaAs/GaAlAs interface form a pn junction in the GaAlAs layer below the emitter and collector area. This reduces the current by several orders of magnitude through the parasitic emitter-substrate (base) diode compared to a GaAs pn junction, due to the higher band gap. For these devices with an effective base width of 0.5 µm, a current gain of 10 in common emitter configuration has been obtained.