Abstract
The relationship between parametric drift and latent damage in ESD gate-stressed MOSFETs is studied. Sub-breakdown damage causes minor characteristic distortion, which may remain undetected until failure. However, such damage is only significant within a narrow stress-voltage window. Oxide breakdown may cause straightforward malfunction (i.e. catastrophic failure) or degraded transistor action. Degraded devices can degenerate further under working voltages (0–10 V), providing a latent failure mechanism. Degradation phenomena are attributed to the intrusion of polysilicon gate-material into the oxide and channel regions. Catastrophically failed and degraded devices are modelled using the PSpice circuit simulation system. The effects of degradation upon CMOS logic operation are also examined.
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