Latency-optimised 3D multi-FPGA system with serial optical interface

Abstract

Multi-FPGA systems (MFSs) are capable of prototyping large SoCs. However, planar 2D MFSs with electrical interconnections have broader spatial distribution and large off-chip delays. One good solution for this problem is to use a three-dimensional (3D) architecture, where multiple FPGAs can be stacked on top of each other rather than being spread across a 2D plane. This provides lower off-chip latency with a smaller footprint. 3D MFS performance can be further improved through reduction in the number of interconnects by employing a serial communication. Nevertheless, electrical interconnects are limited in their performance due to latency. Moving a serial link from electrical domain to optical domain decreases off-chip delays improving the system frequency. Additionally, the selection of MFS routing architecture also has a substantial effect on the system performance. In this paper, we propose a novel 3D MFSs with different routing architectures that employ serialised optical interface improving the system frequency significantly. An experimental architecture evaluation framework and associated CAD tools were developed. The proposed architectures were experimentally evaluated and provided average system frequency gain of 37% across six benchmark circuits.