Abstract
A CMOS integrated circuit test chip (Latch-Up and Radiation Integrated Circuit--LURIC) designed for CMOS latch-up and radiation effects research is described. The purpose of LURIC is (a) to provide information on the physics of CMOS latch-up, (b) to study the layout dependence of CMOS latch-up, and (c) to provide special latch-up test structures for the development and verification of a latch-up model. Many devices and test patterns on LURIC are also well suited for radiation effects studies. LURIC contains 86 devices and related test structures. A 12-layer mask set allows both metal gate CMOS and silicon gate ELA (Extended Linear Array) CMOS to be fabricated. Six categories of test devices and related test structures are included. These are (a) the CD4007 metal gate CMOS IC with auxiliary test structures, (b) ELA CMOS cells, (c) field-aided lateral pnp transistors, (d) p-well and substrate spreading resistance test structures, (e) latch-up test structures (simplified symmetrical latch-up paths), and (f) support test patterns (e.g., MOS capacitors, p/sup +/n diodes, MOS test transistors, van der Pauw and Kelvin contact resistance test patterns, etc.). A standard probe pattern array has been used on all twenty-four subchips for testing convenience.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.