Abstract
Inherent in the structure of bulk CMOS integrated circuits are four-layer parasitic paths that can become activated into a low impedance, high-current state, i.e., latch-up. Activation can be accomplished by photocurrents generated by ionizing radiation or by terminal over-voltage spikes. As loss of functionality or device destruction can result, latch-up is undesirable. This paper describes a method of latchup prevention by the use of n on n+ starting material. A graphical analysis is presented that aids in the understanding of the latch-up mechanism and provides insight into the elimination of that state. Experimental data in support of the model is presented.
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