Abstract
An on-chip charge-collection measurement circuit has been designed and fabricated in a 130 nm bulk CMOS process. Laser testing is used to verify the effectiveness of the on-chip charge-collection circuit technique for characterizing single event charge collection in advanced technologies. The on-chip charge-collection measurement circuit is used as an investigative tool for examining the effects of parasitic bipolar amplification for deep-submicron PMOS devices.
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