Large-Signal Modeling for Nonlinear Analysis of Experimental Devices in 22nm FDSOI Technology

Abstract

The development process of the FDSOI CMOS technology is continuously ongoing to improve the performance for high-frequency applications, especially for power amplification. Meanwhile, customized transistor devices pose difficulties to be integrated fast into the existing foundry’s PDK for nonlinear analysis. This paper thereby presents an empirical large-signal modeling approach for experimental devices in the 22nm FDSOI CMOS. In particular, a versatile mathematical expression for the drain current has been developed which can accurately model various device types. Moreover, the gate charge is computed and modeled by using artificial neural network. The modeling approach has been verified by using the latest hardware in the industry’s 22nm FDSOI with multi-bias S-parameters up to 110 GHz and non-50-Ω large-signal measurements.