Abstract
A folding architecture for a subthreshold CMOS transconductance amplifier is described in the Letter. Good linearity is obtained for an extremely large differential input voltage, without loss in the common-mode voltage range. Theoretical noise analysis indicates a 6 dB improvement in the dynamic range compared to a simple single-pair MOS implementation. A prototype has been fabricated in a 2 µm CMOS process, and experimental results are presented.
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