Large Laminate and Die Coreless Substrate Packaging with Lid Ties

Abstract

Coreless flip chip laminate substrates have shown significant advantages over cored versions in terms of wireability due to the absence of large coarse pitch core vias and accompanying via lands. Resistance to widespread acceptance of coreless has been associated primarily with package manufacturability. Increased warpage tendencies for coreless both at room temperature and thermally have driven packaging techniques such as the use of stiffeners prior to chip join increasing packaging costs. A new low Coefficient of Thermal expansion (CTE) laminate dielectric material is being introduced for coreless substrates. A novel method for packaging using lid ties has been developed to enable this new substrate technology. Lid ties are dots of encapsulation material deposited in an array on the coreless laminate substrate outside the chip area prior to capping. Lid ties have been shown to enable excellent results for manufacturability, quality, and reliability of large die large laminate coreless semiconductor packages. use of lid ties has been introduced at acceptable costs. Assembly and reliability results will be shown. Design parameters related to lid tie patterns impacting reliability will be discussed. Affects of lid ties and lid tie design on test and burn in performance will be reviewed.