Abstract
The process and feasibility verification for a full wafer silicon-on-insulator (SOI) process by using two merged epitaxial lateral overgrowths has been achieved. This process can be used to produce SOI material with a wide range of silicon thicknesses from 0.1 μm to several microns thick and is compatible with three-dimensional circuit integration. Formation of local area SOI islands, formation of vertical wall seed windows, and epitaxial lateral overgrowth from these narrow vertical seeds have been demonstrated. This SOI process has the potential to reduce the defect density and cost of SOI substrates.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.