Laminated process effect of high-density redistributed trace lines on the risk estimation of induced-stress failure for 3D-IC embedded interposer

Abstract

The embedded interposer carrier (EIC) technology for 3D-integrated circuits (3D-ICs) play an important role as a promising candidate to deal with the assembly/bonding processes of thin stacked chip and substrate. However, peeling stress of the interface between stacked via holes and copper-filled through silicon via silicon-based interposer may cause a thermomechanical reliability issue among multi-stacked film EIC architectures. For dealing with this situation, we propose a process-oriented finite element analysis method considering material nonlinear behaviors as well as process flows including process temperature and steps. This method is able to analyze systematically the effect of cycling temperature loads induced during the bonding process. From the result of simulations, it indicates that the curing process of laminated material is the critical step among the entire bonding process. In addition, the material about a compliant interposer is recommend to be a suitable solution for EIC architecture enhancing operational reliability. Furthermore, the thermal stress of each thin film stacked inside EIC structure can be relieved by means of the flexible of the carrier laminate design.