Laminated ferrite modular memory for 150-250-ns cycle operation

Abstract

The small element dimensions obtainable with laminated (monolithic) ferrite memory arrays suggest common packaging of the magnetic and semiconductor components to form compact self-contained modules. Coupling the modules with additional integrated circuit nets makes possible memories of megabit capacity with cycle times in the range of 150 to 250 ns. The modular system is described and evaluated for a 512-word 64-bit-per-word test module. Module operation is 2D, two storage intersections per bit. All circuitry is transformerless to facilitate circuit integration. Word currents are supplied by a diode matrix-complementary bi-polar transistor circuit in each module. Bipolar transistor digit-sense circuitry is shared between modules. A nonreturn-to-zero mode of digiting is utilized to maximize sense signal and minimize cycle time. Factors determining access and cycle times are discussed. Operation uniformity and margin data are given.