Lack of Spatial Correlation in MOSFET Threshold Voltage Variation and Implications for Voltage Scaling

Abstract

Due to increased variation in modern process technology nodes, the spatial correlation of variation is a key issue for both modeling and design. We have created a large array test-structure to analyze the magnitude of spatial correlation of threshold voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</i> ) in a 180 nm CMOS process. The data from over 50 k measured devices per die indicates that there is no significant within-die spatial correlation in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</i> . Furthermore, the across-chip variation patterns between different die also do not correlate. This indicates that Random Dopant Fluctuation (RDF) is the primary mechanism responsible for <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</i> variation and that relatively simple Monte Carlo-type analysis can capture the effects of such variation. While high performance digital logic circuits, at high <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VDD</i> , can be strongly affected by spatially correlated channel length variation, we note that subthreshold logic will be primarily affected by random uncorrelated <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</i> variation.