K-nearest neighbor algorithm implementation on FPGA using high level synthesis

Abstract

The K-Nearest Neighbor (K-NN) algorithm is one of the most common classification algorithms and widely used in pattern recognition and data mining. K-NN hardware acceleration is necessary for applications with massive high-dimensional data. High level synthesis (HLS) is an increasingly adopted technique in digital circuit design, which can help to raise the abstraction levels. In this paper, we exploit the parallelism and pipelining opportunities and apply the memory-mapped AXI4-Master Interface to implement K-NN on an FPGA using HLS. The evaluation result shows that our HLS-based solution is 35.1× faster than a general purpose processor (GPP) based implementation, and comparable to hardware description language (HDL) based implementations, while our HLS-based solution largely reduces the development complexity and cost.