Abstract
Key-value Store (KVS) is one of the most important components in trading system for performing search operations. High Level Synthesis (HLS) provides a new flow for design of Field Programmable Gate Array (FPGA) systems. We describe a novel low latency, high throughput, memory efficient KVS block designed using conventional Verilog flow as well as High Level Synthesis flow and targeted to FPGA technology. We compare these two flows for designing KVS. Substantial advantage in gained in terms of productivity using HLS. The time for implementing in HLS is just 18% as compared to Verilog flow though the resource utilization in case of hand coded Verilog is better. The design shows promising performance numbers indicating that more complex FPGA systems could be designed using HLS.
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