(Keynote) Unipolar CMOS Logic for Post-Si ULSI and TFT Technologies

Abstract

This article introduces a novel "unipolar CMOS" logic circuit scheme based on an inverter that consists of two N-channel (or P-channel) enhancement-mode MOSFET's, where one has a positive threshold voltage and the other a negative threshold voltage. In contrast, the conventional CMOS inverter consists of a N-channel and a P-channel MOSFET, where the P-channel MOSFET can significantly limit its overall switching speed, due to the low hole mobility, especially for such III-V semiconductors as InAs, GaInAs, and GaAs, where there is a huge disparity between the electron and the hole mobility. This mobility mismatch issue is even more severe for thin-film transistors that are difficult to make either p-channel or n-channel transistors, such as zinc oxide, amorphous Si, and many organic transistors. The implementation of the "unipolar CMOS" logic will obviate the need for a P-channel MOSFET in the CMOS inverter switch, and takes full advantage of the higher drive current that N-channel MOSFET's offer. .