Kernel-Windowed SDFT Based Frequency-Locked Loop for Capacitance Sensing on an FPGA

Abstract

Sliding discrete Fourier transform with kernel windowing technique is proposed for frequency estimation of periodic signals that can be applied to capacitance sensing. SDFT is an efficient technique to compute <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${N}$ </tex-math></inline-formula> -point DFT of a signal by sliding the rectangular window one sample at a time. In the proposed work Hanning and Blackman windows replace rectangular window of SDFT to reduce the spectral leakage and increase the mainlobe width of the spectra. The concept of increased mainlobe width of the SDFT spectra has been exploited to increase the operating range of the frequency-locked loop. Kernels of these windows have been computed with certain coefficients and incorporated in the FLL to increase the operating range which increases the estimation input signal frequency. Designed FLL with Hanning window having bin index <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k} = 1$ </tex-math></inline-formula> estimates frequency from 4 to 56 kHz while with Blackman window estimates frequency from 6 to 75 kHz. The proposed scheme with kernel windowing has been implemented in FPGA and verified for enhanced performance. The experimental investigation on the proposed technique is validated for discrete capacitance sensing with maximum frequency estimation error of 0.054 and liquid level measurement of 0 - 13.5 cm with a sensitivity of 4.435 pF/mm. This method provides wide range of frequency estimation which results in wide range of capacitance measurement.