Keeping runtimes down in embedded gate array layout checks

Abstract

Embedded gate arrays can reduce the initial costs of producing ASICs but raise physical verification issues that demand the effective use of hierarchical tools. The real issue with verification of the base array is with layout versus schematic (LVS) checks. The use of a regular array makes it similar to a memory with the disadvantage that, unlike a memory, none of the blocks are connected. Labeling a multitude of nets for correspondence may well help in checking the base, but these bases will be programmed at some point and will need to be LVS verified again, without any manual manipulation of the layout as, once in production use, schedules will be very tight. In the case of a base array, the netlist is algorithmically generated and typically reflects the architecture of the device from a design standpoint while the layout is typically structured for the most efficient placement of the devices to minimise area.