Abstract
Power density constraints are limiting the performance improvements of modern CPUs. To address this we have seen the introduction of lower-power, multi-core processors, but the future will be even more exciting. In order to stay within the power density limits but still obtain Moore's Law performance/price gains, it will be necessary to parallelize algorithms to exploit larger numbers of lightweight cores and specialized functions like large vector units. Example technologies today include Intel's Xeon Phi and GPGPUs.Track finding and fitting is one of the most computationally challenging problems for event reconstruction in particle physics. At the High Luminosity LHC, for example, this will be by far the dominant problem. The need for greater parallelism has driven investigations of very different track finding techniques including Cellular Automata or returning to Hough Transform. The most common track finding techniques in use today are however those based on the Kalman Filter [2]. Significant experience has been accumulated with these techniques on real tracking detector systems, both in the trigger and offline. They are known to provide high physics performance, are robust and are exactly those being used today for the design of the tracking system for HL-LHC.Our previous investigations showed that, using optimized data structures, track fitting with Kalman Filter can achieve large speedup both with Intel Xeon and Xeon Phi. We report here our further progress towards an end-to-end track reconstruction algorithm fully exploiting vectorization and parallelization techniques in a realistic simulation setup.
Highlights
Pile-up (PU) represents a challenge for HEP event reconstruction, both in terms of physics performance and in terms of processing time
For PU values exceeding 100, as expected at the High Luminosity LHC (HL-LHC), the time needed for event reconstruction diverges (Fig. 1); due to power density limitations to Moore’s law, such a large increase is not sufficiently compensated by an increase in CPU clock frequency
The main reason for this choice is that it shares many features with more conventional architectures, like the Intel Xeon, so that we can optimize and test the algorithm performance on both architectures at the same time; there is no real prejudice on the choice of the architectures and in the future we plan to explore other options, including GPGPUs
Summary
Pile-up (PU) represents a challenge for HEP event reconstruction, both in terms of physics performance and in terms of processing time. We tackle the problem starting from the the most challenging algorithm, track reconstruction; tracking is by far the most time consuming process in event reconstruction (Fig. 1) so that, if the proposed approach does not work in this case, there is little to gain from the rest of event reconstruction.
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