${K}$ -Cyclic Schedules and the Worst-Case Wafer Delay in a Dual-Armed Cluster Tool

Abstract

In a cluster tool for semiconductor manufacturing, a wafer waits within a chamber after processing until it is unloaded by the robot. Such wafer delays degrade wafer quality due to residual gases and heat, even cause quality failures. A cluster tool mostly operates in a ${K}$ -cyclic schedule, where an identical timing pattern repeats for each ${K}$ cycles, because of sporadic disruptions in process times or robot task times and the closed-architecture of the tool scheduler. In addition, it is hard to predict the ${K}$ -cyclic schedule that the tool will reach. Such a ${K}$ -cyclic schedule makes wafer delays at each chamber repeat ${K}$ different values. Therefore, such variability of wafer delays increases the risk of quality failure. Therefore, we examine the maximum wafer delay among all possible ${K}$ -cyclic schedules called the worst-case wafer delay in this paper. We first characterize the maximum cyclicity ${K}$ of tool schedules. We then develop closed-form formulas for most frequently used wafer flow patterns and an optimization model that computes the worst-case wafer delay. We also identify factors that affect the worst-case wafer delay and their influences by experiments. Finally, we suggest tool operation guidelines for lowering the worst-case wafer delay.