Junctionless Accumulation Mode Ferroelectric FET (JAM-FE-FET) for High Frequency Digital and Analog Applications

Snehlata Yadav,Rajeshwari Pandey,Sonam Rewari

doi:10.1007/s12633-021-01537-y

Abstract

In this paper, a Junctionless Accumulation Mode Ferroelectric Field Effect Transistor (JAM-FE-FET) has been proposed and assessed in terms of RF/analog specifications for varied channel lengths through simulations using TCAD Silvaco ATLAS simulator, using the Shockley-Read-Hall (SRH) recombination, ferro, Lombardi CVT, fermi and LK models. Major analog metrics like transconductance (gm), intrinsic gain (AV), output conductance (gd), and early voltage (VEA) are obtained for the JAM-FE-FET arrangement. The proposed structure shows an improvement in parameters like gm, Ion/Ioff, Av, TGF by 6.82%, 27.95%, 5.2%, 38.83% respectively. Further, frequency analysis of the proposed device is performed and several critical RF parameters like fT, TFP, GFP, and GTFP have been observed to be enhanced by 6.89%, 11.38%, 13.65%, 12.01% respectively. Thus, the Junctionless accumulation mode ferroelectric FET (JAM-FE-FET) arrangement has been found to have superior analog and RF performance when compared to Junctionless ferroelectric FET(JL-FE-FET). As a result, the JAM-FE-FET device presented here can be contemplated a good contender for applications in high-frequency systems.

Highlights

Various MOSFET structures have been realized over the last few decades, and their scaling has been quite successful down to the nano scale, resulting in a significant increase in performance [1],[2]
In this research article, a simulation-based comparative analysis is done for proposed JAM-field effect transistors (FE-FETs) with JL-FE-FET
In comparison to JL-FE-FET, the subthreshold swing is lowered by 20.37%

Summary

Introduction

Various MOSFET structures have been realized over the last few decades, and their scaling has been quite successful down to the nano scale, resulting in a significant increase in performance [1],[2]. To address the aforementioned issues, a new modified structure known as the JAM FET was introduced [11], which has highly doped S/D regions and decreased doping in the channel, resulting in reduced mobility deterioration [12] Another major issue that has arisen as a result of shrinking and the increased density of transistors on a chip is higher power consumption and heat dissipation, both of which slow down data processing rate [13],[14]. Quantum mechanical effect has not been considered and the channel thickness and ferroelectric thickness are restricted to 20 nm and 10nm respectively Motivated by these coexisting research findings, a novel device structure, JAM-FE-FET is reported in this paper.

Device fabrication and calibration

Results & Discussions

Conclusion

Findings

References: