Abstract
We developed a technique to study junction leakage in an advanced complementary metal oxide semiconductor (CMOS) device using scanning capacitance microscopy (SCM). Devices marginally failing for leakage testing were particularly selected. Progressive metal cuts and direct probing were performed to isolate the affected test structure. A reverse bias voltage was applied across the n-well and p-type diffusion layer. The current-voltage (I--V) curves obtained confirmed presence of a leakage path between the n-well and the p+ diffusion. The SCM data revealed that the marginal leakage current was due to higher n-well doping level of the device compared to the control unit. Furthermore, the diode-tunneling equation was simulated and the results were in good agreement with empirical data. The SCM technique can, therefore, be very useful for defect localization and physical failure analysis of samples without interconnects or electrodes to aid in root cause identification.
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