Junction and doping-free transistors for future computing

Abstract

Continued down-scaling of device dimensions poses severe challenges and difficulties for complementary metal-oxide semiconductor technology, particularly fabrication complexities, process variability, and short channel effects. These challenges mainly arise due to abrupt doping profile requirement at junctions and random dopant fluctuations (RDFs). Recently, the junctionless field-effect transistors (JLFETs), also known as gated resistors, have widely attracted attention, as they do not require formation of any metallurgical junctions (P-N, N+-N, or P+-P) and doping concentration gradient throughout the device. Thus, they relax abrupt doping profile requirements and greatly simplify the fabrication process. A key requirement for JLFETs is the formation of a semiconductor layer that should be thin and narrow enough to be depleted when the JLFET is in off-state. At the same time, semiconductor layer should be doped enough to achieve an adequate amount of drain current in on-state. Therefore, JLFETs are generally made of heavily doped silicon nanowires. The heavily doped nature of JLFETs causes certain problems, and to address them, the concept of doping-free (dopingless) JLFETs was recently proposed. In this chapter, detail study of both junction-free and doping-free transistors are presented based on 2-D device simulation with model calibrated to experimental data.