Junction and Device Characteristics of Gate-Last Ge p- and n-MOSFETs With ALD- $\hbox{Al}_{2}\hbox{O}_{3}$ Gate Dielectric

Abstract

In this paper, we investigated the characteristics of Ge junction diodes and gate-last p- and n-metal-oxide-semiconductor field-effect transistors with the atomic-layer-deposited- Al2O3 gate dielectrics. The magnitudes of the rectifying ratios for the Ge p+-n and n+-p junctions exceeded three and four orders of magnitude (in the voltage range of plusmn1 V), respectively, with accompanying reverse leakages of ca. 10-2 and 10-4 A ldr cm-2, respectively. The site of the primary leakage path, at either the surface periphery or junction area, was determined by the following conditions: 1) the thermal budget during dopant activation, and 2) whether forming gas annealing (FGA) was employed or not. In addition, performing FGA at 300degC boosted the device on-current, decreased the Al2O3/Ge interface states to 8 times 1011 cm-2 ldr eV-1, and improved the reliability of bias temperature instability. The peak mobility and on/off ratio reached as high as 225 cm2 ldr V-1 ldr s-1 and > 103, respectively, for the p-FET (W/L = 100 mum/4 mum), while these values were less than 100 cm2 ldr V-1 ldr s-1 and ca. 103, respectively, for the n-FET (W/L = 100 mum/9 mum). The relatively inferior n-FET performance resulted from the larger source/drain contact resistance, higher surface states scattering, and lower substrate-doping concentration.