Abstract
This paper describes briefly the main architectural and design features of the Josephson Signal Processor (JSP), including its data flow, basic circuit arrangement, and packaging concept. Preliminary partitioning has indicated that, using a 5-µm “single turn logic” technology, the JSP—consisting of about 5000 cells (each with four Josephson junctions) of logic, about 150K bits of nondestructive read out (NDRO) memory, 256K bits of destructive read out (DRO) memory, and 6K bits of read only memory (ROM)—can be packaged in about 20 modules, occupying about 60 cc and consuming about 500 mW of power. The target cycle time for the JSP is 5 ns, with the NDRO and DRO memories having an access/cycle time of about 2.5/4 and 15/30 ns, respectively. Using a 2.5-µm “current injection logic” technology, the JSP—consisting of about 9000 three-junction and 5000 two-junction interferometers—can be packaged in seven modules occupying about 12 cc and will consume about 250 mW of power. The target cycle time for this technology is about 2 ns, with the NDRO and DRO memories having access/cycle times of 0.9/1.4 and 15/30 ns, respectively.
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