Josephson-CMOS hybrid memory with ultra-high-speed interface circuit

Abstract

In this paper we report our recent progress in realizing a Josephson-CMOS hybrid random-access memory. We have established a 4 K CMOS device model based on low-temperature experimental data on discrete MOS devices. We implemented an ultra-high-speed interface circuit to amplify millivolt-level Josephson input signals to volt-level signals for CMOS circuits. The interface circuit includes a Josephson series-array preamplifier and an ultra-fast hybrid Josephson-CMOS amplifier. Simulation and optimization of the interface circuit have predicted a delay of less than 60 ps. We have designed and fabricated the interface circuit using the 0.25 /spl mu/m National Semiconductor Corporation (NSC) process for the CMOS chip, and the UC Berkeley 6.5 kA/cm/sup 2/ Nb process for the Josephson junction (JJ) chip. The functionality of the interface circuit has been tested and proved by wire-bonding the CMOS chip to the JJ chip. We also demonstrate the design and fabrication of a model 64-kbit Josephson-CMOS hybrid memory; this circuit includes the ultra-high-speed interface, address buffers, word line decoders, 3 T DRAM-type cells, and Josephson sensing circuits; these are fabricated using the 0.25 /spl mu/m NSC CMOS process and the UC Berkeley Nb process. Subnanosecond access time is predicted by a conservative simulation that used a room-temperature model for the CMOS. We plan a stacked-chip structure using very short wire bonding with which we will be able to measure subnanosecond access times.