Abstract
Improving SRAM minimum operating voltage (V min ) in scaled process nodes requires characterization of different failure mechanisms. Persistent errors caused by random variations and intermittent errors caused by random telegraph noise (RTN) both contribute to bitcell failure. Random V th shift was measured for 32,000 in-situ SRAM cells in both 28nm bulk and FDSOI processes due to both random variations and RTN, and dynamic writeability was measured by two different write modes that accentuate different RTN behaviour. Measured distribution parameters of both random variation and RTN were used to calibrate an accelerated Monte Carlo simulation that predicts a V min difference due to RTN. Measurements show that while FDSOI technology reduces random variation by approximately 27% compared to bulk, similar RTN amplitudes slightly increase bitcell susceptibility to failures caused by RTN.
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