Joint and Separate Minimization of Multilevel Representations of Boolean Function Systems

Abstract

The results of experimental studies of the effectiveness of programs for minimizing multilevel representations of systems of Boolean functions performed during the synthesis of combinational circuits in the design library of custom CMOS VLSI are presented. The efficiency of joint and separate minimization programs using Shannon expansions for constructing multilevel representations of systems of fully defined Boolean functions in the form of interconnected systems of logical equations — complete or abbreviated formulas of Shannon expansion or formulas corresponding to Boolean networks is investigated. A comparison is made with the results of experiments performed for various types of joint minimization only. A comparison is also made with the results of solutions obtained by the program of joint and separate minimization of Boolean function systems in the DNF class. It is shown that the use of joint minimization of multi-level representations makes it possible to obtain circuits of a smaller area more often, and the use of a separate one — circuits with a lower delay.