Jitter-suppressed low-power 2.5 Gbit/s clock anddata recovery IC without high-Q components

Abstract

A 2.5 bit/s monolithic clock and data recovery (CDR) IC using a PLL technique is fabricated using Si bipolar technology. The CDR IC provides suppressed jitter characteristics with a low power consumption. To our knowledge, this is the first report of a single-chip 2.5 Gbit/s CDR IC, the jitter characteristics of which meet all three types of STM-16 jitter specifications described in ITU-T recommendations.