Jitter issues in clock conditioning with FPGAs

Abstract

Embedded Delay Locked Loops (DLLs) and Phase Locked Loops (PLLs) are available as hard-macros in the latest Field Programmable Gate Arrays. The main features offered by DLLs and PLLs are clock phase de-skewing, frequency synthesis (multiplication or division) and jitter filtering. The clock signal at the output of a DLL or a PLL has a phase noise (or jitter), which has to be taken into account in timing sensitive applications, such as analog-to-digital conversion, time measurements or high-speed serial links. In this work we present the results of jitter analysis conducted on PLLs and DLLs embedded in a Xilinx Virtex 5 FPGA. We explored different configurations (clock multiplication and clock network de-skew) of PLLs and DLLs, at different frequencies.