ITimerM

Abstract

As designs continue to grow in size and complexity, EDA paradigm shifts from flat to hierarchical timing analysis. In this paper, we propose compact and accurate timing macro modeling, which is the key to achieve efficient and accurate hierarchical timing analysis. Our macro model tries to contain only a minimal amount of interface logic. For timing graph reduction, we propose anchor pin insertion and deletion by generalizing existing reduction techniques. Furthermore, we devise a lookup table index selection technique to achieve high model accuracy over the possible operating condition range. Compared with two common models used in industry, extracted timing model and interface logic model, our model has high model accuracy and small model size. Based on the TAU 2016 timing contest on macro modeling benchmark suite, our results show that our algorithm delivers superior efficiency and accuracy: Hierarchical timing analysis using our model can significantly reduce runtime and memory compared with flat timing analysis on the original design. Moreover, our algorithm outperforms TAU 2016 contest winner in model accuracy, model size, model usage runtime and memory.