Issues and Challenges of Cleaning for Nano-Scale NAND Flash Memory Manufacturing

Abstract

In comparison to other IC devices, the unique device structure of a flash memory is a floating gate as a memory cell unit. One of critical steps of the flash memory process integration is the wet etch process of effective field oxide which affects the coupling ratio and the threshold voltage of a cell transistor. Since the gate of a flash memory cell is composed of multi-layers, the gate sidewall damage should be minimized with non-selective and minimal loss during the clean after the gate etch. As contacts and trenches shrink to nano-scale, highly selective and damage-free cleaning should be developed to minimize sidewall loss and prevent pattern collapse. Since complete global and local planarization is required to satisfy stringent requirements of nano-lithography, the number of CMP processes increase gradually. During the cleaning step after the CMP, slurry particles and residues must be removed completely.