Abstract
Wafer-level isotropic etching of silicon with XeF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gas has been investigated for microelectromechanical-system (MEMS) fabrication. Because of the large exposed silicon area in the wafer-level process, XeF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gas diffusion in the wafer-level process is different from the chip-level process. The silicon etch rate for the wafer-level XeF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> process is much smaller than chip-level XeF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> etching. Additionally, the silicon etch rate drops off as the etching time increased. The aperture size effect is apparent in the wafer-level XeF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> processing. However, for etching windows with a large size, the aperture size effect will be minimized. Both vertical and lateral aperture size effects depend on the number of etch cycle. Although slight anisotropy is also observed, wafer-level XeF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> etching shows a better isotropy than the chip-level process. Compared with the chip-level process, wafer-level XeF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> etching shows a large etch rate for SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . The etch selectivity between silicon and SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> is lower than 1000:1. Based on the characteristics of XeF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> etching, the layout design rule for the MEMS device with XeF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> releasing is developed and demonstrated.
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