Abstract
ISFETs have been fabricated using a modified CMOS silicon-gate 5 μm P-well process. The technology flow and ISFET cross sections are designed with a view to achieving as low a light sensitivity as possible. Three different ISFET structures are suggested; they are simulated using SUPREM4 and PISCES2B to determinate influence of the channel and drain-source areas on the light sensitivity of ISFETs and these structures have been fabricated. The light response of one structure (MOSFET type) is measured at a probe station. The ISFET is fabricated with an operational amplifier connected as a follower, a bias (band-gap based) generator and a temperature sensor based on the temperature-dependent current source. The whole circuit needs only four wires, e.g., VCC, GND, OUT and TEMP.
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