Abstract
Large-scale neuromorphic hardware systems typically bear the trade-off between detail level and required chip resources. Especially when implementing spike-timing dependent plasticity, reduction in resources leads to limitations as compared to floating point precision. By design, a natural modification that saves resources would be reducing synaptic weight resolution. In this study, we give an estimate for the impact of synaptic weight discretization on different levels, ranging from random walks of individual weights to computer simulations of spiking neural networks. The FACETS wafer-scale hardware system offers a 4-bit resolution of synaptic weights, which is shown to be sufficient within the scope of our network benchmark. Our findings indicate that increasing the resolution may not even be useful in light of further restrictions of customized mixed-signal synapses. In addition, variations due to production imperfections are investigated and shown to be uncritical in the context of the presented study. Our results represent a general framework for setting up and configuring hardware-constrained synapses. We suggest how weight discretization could be considered for other backends dedicated to large-scale simulations. Thus, our proposition of a good hardware verification practice may rise synergy effects between hardware developers and neuroscientists.
Highlights
Computer simulations have become an important tool to study cortical networks (e.g. Markram et al, 1997; Brunel, 2000; Morrison et al, 2005, 2007; Brette et al, 2007; Johansson and Lansner, 2007; Vogelstein et al, 2008; Kunkel et al, 2011; Yger et al, 2011)
Synaptic weights of the FACETS wafer-scale hardware system (Schemmel et al, 2010) have a 4-bit resolution. We show that such a weight resolution is enough to exhibit learning in a neural network benchmark for synchrony detection
CONFIGURATION OF Spike-Timing Dependent Plasticity (STDP) ON DISCRETE WEIGHTS In this study, we demonstrate generic strategies to configure STDP on discrete weights as, e.g. implemented in neuromorphic hardware systems
Summary
Computer simulations have become an important tool to study cortical networks (e.g. Markram et al, 1997; Brunel, 2000; Morrison et al, 2005, 2007; Brette et al, 2007; Johansson and Lansner, 2007; Vogelstein et al, 2008; Kunkel et al, 2011; Yger et al, 2011). Markram et al, 1997; Brunel, 2000; Morrison et al, 2005, 2007; Brette et al, 2007; Johansson and Lansner, 2007; Vogelstein et al, 2008; Kunkel et al, 2011; Yger et al, 2011) While they provide insight into activity dynamics that can not otherwise be measured in vivo or calculated analytically, their computation times can be very time-consuming and unsuitable for statistical analyses, especially for learning neural networks (Morrison et al, 2007). Neuromorphic hardware systems are an alternative to von Neumann computers that alleviates these limitations Their underlying VLSI microcircuits are especially designed to solve neuron dynamics and can be highly accelerated compared to biological time (Indiveri et al, 2011). Many neuromorphic hardware systems are developed for operation in real-time to be applied in sensor applications or medical implants (Fromherz, 2002; Vogels et al, 2005; Levi et al, 2008)
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