IR-level annotation strategy dealing with aggressive loop optimizations for performance estimation in native simulation

Abstract

Originally developed for purely functional verification of software, native or host compiled simulation [6] has gained momentum, thanks to its considerable speedup compared to instruction set simulation (ISS). To obtain a performance model of the software, non-functional information is computed from the target binary code using low-level analysis and back-annotated into the high-level code used to generate it. This annotated functional model is then natively compiled and executed on the host machine for fast software timing [8] estimations. Back-annotating at the right place needs a mapping between the binary instructions and the high-level code statements. So, it is necessary to decide at which stage of the software compilation process the information is back-annotated. There are three possibilities: in the original source code ([7]), in the host binary code ([3]), or in the compiler intermediate representation (IR) ([8], [2]). As compilers perform many optimizations to enhance software performance, the source code and the binary code structures may be radically different. In this work, we define a mapping approach between the compiler's IR and the binary control flow graph (CFG) when a high-level of compiler optimizations (eg. O3 in gcc) is used. Our approach handles aggressive compiler optimizations such as loop unrolling without having to introduce any modification to the compiler.