IR-drop modeling and reduction for high-performance printed circuit boards

Abstract

In this paper, IR drop reduction of high-performance printed circuit boards (PCBs) is discussed. The IR drop of multilayer PCB is analyzed by using model decomposition and adaptive mesh. It is shown that both the via contact of voltage regulator module (VRM) and the copper planes produce significant IR drop. A star topology is proposed for IR drop reduction, which can significantly reduce the resistance introduced by the via contact of VRM and the copper planes. Star topology can reduce the IR drop by about 50%. Furthermore, the efficiency of through via design on the IR drop reduction for multi-plane structures is analyzed. Through via design rules and radial via array are presented for maximum IR drop reduction. With proper design of through vias, the IR drop of N planes can be reduced to 1/N of that of a single plane. Using star topology in multi-plane structure, the IR drop of PCBs with current demand of 100+A can be kept within a few tens of millivolt.