Abstract
The design of power grid network is critical in scaled technologies for reliable operation of a circuit. This paper presents novel CAD techniques for mitigating IR-drops in FPGAs. Placement and routing techniques are developed in the paper for improving the voltage profile of the power grid network. The proposed techniques not only improve the minimum voltage at any node in the FPGA power grid, but also reduces the variance of the supply voltage distribution across all the nodes in the power grid. An improvement of up to 7% in the minimum V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> and up to 66% reduction in standard deviation of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> is obtained from the design technique proposed in this paper.
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