IP core logic fault test simulation environment

Abstract

A low-level logic fault test simulation environment for embedded systems directed specifically towards application-specific integrated circuits (ASICs) and intellectual property (IP) cores is proposed in the paper. The developed simulation environment emulates a typical builtin self-testing (BIST) architecture with automatic test pattern generator (ATPG) that sends its outputs to a circuit (core) under test (CUT) and the output streams from the CUT are fed into an output response analyzer (ORA). The paper delineates the development of the test architecture, test application and fault injection including the relevance of the logic fault simulator.in great details. Some results on simulation on specific IP cores designed using combinations from ISCAS 85 combinational and ISCAS 89 sequential benchmark circuits are provided as well for evaluation.