Abstract
An algorithmic RAM-based IP address lookup method called bit-shuffled trie is presented. By rearranging the bits of the prefixes, memory efficient index tables can be constructed to support IP address lookup. The address lookup engine can be implemented using pipelined architecture with simple processing logic. The proposed method has superior memory efficiency. The memory cost for a 474K prefixes IPv4 routing table is only 1.1MB, and the memory cost for a 215K 64-bit prefixes IPv6 routing table is about 1.7MB. The exceptional memory efficiency of the proposed method allows us to implement the IP address lookup engine for both IPv4 and IPv6 on a single FPGA device. Incremental updates to the routing table can be handled efficiently. On average, about 8 memory-write operations to the data structures are required to process an insertion or deletion.
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