Ionization Model for Negative Capacitance in Low-Mobility Semiconductors such as Amorphous Chalcogenides

Abstract

A model to explain negative incremental ac capacitance has been developed, under the assumption that excess electrons and holes are generated in approximately equal numbers due to fairly general ionization processes such as impact ionization, localized Joule heating, or photoionization. Impact ionization is treated specifically. The motion of the excess carriers in a two-terminal bulk device gives rise to space charges which enhance the field near the electrodes. The finite times required for redistribution of the space charge and motion of the carriers through the device give rise to a lag τ of the external circuit current behind the voltage. The magnitude of the current component that lags by π/2 is proportional to ω if ωτ≪1. Thus if ωτe and ωτh≪1, where τe and τh are the electron and hole transit times, negative contributions to the ac capacitance are expected. A relation between the negative capacitance and the current-voltage characteristic is given, and this relation can provide an estimate of the order-of-magnitude of mobility for the lower-mobility charge carrier. Possible application of this model to the negative incremental capacitance observed in amorphous semiconductor switching devices is discussed, and data in the literature for a chalcogenide alloy are shown to fit the model, with an exponential dependence upon voltage. An effective carrier drift mobility of 3×10−4 cm2/V·sec is obtained.