Ion Implanted Phosphorous for 4H-SiC VDMOSFETs Source Regions: Effect of the Post Implantation Annealing Time

Abstract

Van der Pauw devices have been fabricated by double ion implantation processes, namely P+ and Al+ co-implantation. Similarly to the source area in a SiC VD-MOSFET, a 5 × 1018 cm-3 P plateau is formed on the top of a buried 3 × 1018 cm-3 Al distribution for electrical isolation from the n- epilayer. The post implantation annealing temperature was 1600 °C. Annealing times equal to 30 min and 300 min have been compared. The increase of the annealing time produces both an increase of electron density as well as electron mobility. For comparison a HPSI 4H-SiC wafer, 1×1020 cm-3 P+ ion implanted and 1700 °C annealed for 30 min was also characterized.